If Breakthrough Starshot can achieve its goal of delivering small silicon chip payloads to Proxima Centauri or other nearby stars, it will be because we’ve solved any number of daunting problems in the next 30 years. That’s the length of time the project’s leaders currently sketch out to get the mission designed, built and launched, assuming it survives its current phase of intense scrutiny. The $100 million that currently funds the project will go into several years of feasibility analysis and design to see what is possible.
That means scientists will work a wide range of issues, from the huge ground-based array that will propel the payload-bearing sails to the methods of communications each will use to return data to the Earth. Also looming is the matter of how to develop a chip that can act as all-purpose controller for the numerous observations we would like to make in the target system.
If the idea of a spacecraft on a chip is familiar, it’s doubtless because you’ve come across the work of Mason Peck (Cornell University), whose work on the craft he calls ‘sprites’ has appeared many times in these pages (see, for example, Sprites: A Chip-Sized Spacecraft Solution). Both Peck and Harvard’s Zac Manchester, who worked in Peck’s lab at Cornell, have been active players in Breakthrough Starshot’s choice of single-chip payloads and continue to advise the project.
Image: A small fleet of ‘sprites,’ satellites on a chip, as envisioned in low Earth orbit. Can single-chip spacecraft designs now be developed into payloads for an interstellar mission? Credit: Space Systems Design Studio.
Meanwhile, NASA itself has been working with the Korea Institute of Science and Technology (KAIST) on the design of single-chip spacecraft. A key issue, discussed at the International Electron Devices Meeting in San Francisco in early December, is how to keep such a chip healthy given the hazards of deep space. For Starshot, the matter involves not just the few minutes of massive acceleration (over 60,000 g’s) of launch from Earth orbit, but the 20 years of cruise time at 20 percent of the speed of light before reaching the target star.
The first part of the question seems manageable, as hardening electronics against huge accelerations is an area well studied by the military, so data are abundant. The cruise phase, though, opens up concerns about radiation. According to KAIST’s Yang-Kyu Choi, interstellar radiation can degrade performance through the accumulation of positively charged defects in the silicon dioxide depths of the chip. Such defects can produce anomalous current flow and changes to the operation of critical transistors. The matter of malfunctioning chips is discussed in this recent story in IEEE Spectrum.
At the San Francisco meeting, self-healing chips were the theme, drawing on work that comes out of the 1990s that showed heating could help radiation sensors recover their functionality. Mixing this with work on flash memory out of Taiwan’s Macronix International, an integrated device manufacturer in the Non-Volatile Memory (NVM) market, the new NASA study uses concepts developed at KAIST to make on-chip healing more efficient. From the IEEE story:
This study uses KAIST’s experimental “gate-all-around” nanowire transistor. Gate-all-around nanowire transistors use nanoscale wires as the transistor channel instead of today’s fin-shaped channels. The gate, the electrode that turns on or off the flow of charge through the channel, completely surrounds the nanowire. Adding an extra contact to the gate allows you to pass current through it. That current heats the gate and the channel it surrounds, fixing any radiation-induced defects.
It might seem natural to simply provide more shielding for the chip during the two decades of interstellar cruise, but shielding adds mass, a critical issue when trying to drive a payload to a significant fraction of the speed of light. Thus the self-healing alternative, which assumes potential damage but provides self-analysis of the problem and heat inside the chip to work the healing magic. We also gain from the standpoint of further miniaturization — at scales of tens of nanometers, nanowire transistors are significantly smaller than the kind of transistors on chips currently used in spacecraft, adding savings in chip size and weight.
According to the IEEE report, KAIST’s “gate-all-around” device is likely to see wide production in the early 2020s at it begins to replace the older FinFET (Fin Field Effect Transistor) technologies. From the standpoint of single-chip spacecraft, it’s heartening to learn that radiation repairs can be made over and over, with flash memory recovered up to 10,000 times. A scenario emerges in which a chip on an interstellar flight can be powered down, heated internally to restore full performance, and then restored to service.
Pondering interstellar performance for chips that weigh no more than a gram is cause for reflection. Within just a few years we’ve gone from the idea of massive fusion-driven designs like Project Daedalus to payloads smaller than smartphones. The idea invariably brings to mind Robert Freitas’ concept of a ‘needle’ probe that could be sent in swarms to nearby stars, loaded with nanotech assemblers that would construct scientific instruments and communications devices out of material they found in the destination system.
It wasn’t so long ago that former NASA administrator Dan Goldin was speaking of a probe as light as a Coke can, but the Freitas probe and Breakthrough Starshot go well beyond that. The trick here is not getting too far ahead of the curve of technological development. With a 30-year window, Starshot can anticipate breakthroughs that will solve some of its key challenges, but relying on the future to plug in a solution doesn’t always go as planned. Thus it’s heartening to see potential answers to the cruise problem already beginning to emerge.